ONFI Spec Analysis Part 1: Architecture and Protocol Basics

The Open NAND Flash Interface (ONFI) is a crucial industry standard that defines a common interface for NAND flash memory flakes and controllers. This post kicks off a series exploring the intricacies of the spec.

1. Why ONFI Matters

Before ONFI, every NAND vendor had subtle differences in timing and pinouts. ONFI standardized this, allowing a single controller design to support multiple vendors (Micron, SK Hynix, Intel, etc.).

2. Key Architecture Elements

• Target: A NAND device that receives commands.
• LUN (Logical Unit): The smallest unit that can execute commands independently.
• Block & Page: The structural hierarchy of data storage.

3. Signal Definitions

ONFI uses a specific set of signals to manage data flow:

• ALE (Address Latch Enable): Controls address input.
• CLE (Command Latch Enable): Controls command input.
• RE#/WE#: Read/Write enable toggles.

4. The Parameter Page

One of ONFI’s greatest contributions is the Parameter Page. It allows the controller to “query” the NAND device to discover its capacity, timing modes, and features automatically.

Stay tuned for Part 2, where we will dive into High-Speed Data Interfaces and NV-DDR3 timing.